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7-level of Asymmetric MLI with Reduced Number of Switching Devices Structure for High Power-Density Achievement Using Pareto-Front Method

  • Asmarashid Ponniran*
  • , Mohd Hafizie Yatim
  • , Mohd Amirul Naim Kasiran
  • , Mohamad Kamil Romai Noor
  • , Rini Nur Hasanah
  • , Waru Djuriatno
  • *Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a 7-level asymmetric multilevel inverter (AMLI) utilizing a 5-level reduced number of switching devices (RNSD) configuration, optimized for high power-density achievement. The proposed RNSD configuration is modulated with Sinusoidal Pulse Width Modulation (SPWM), achieving high output voltage quality and minimized total harmonic distortion (THD). Waveform quality is verified experimentally (THD: 4.4%) and through simulation (THD: 0.8%), adhering to IEEE Std 519-1992 requirements. A Pareto-Front analysis validates the topology’s superior performance relative to the conventional 7-level cascaded H-bridge (CHB). Operating across a switching frequency range of 2 kHz to 500 kHz, the design achieves a peak power density of 4.46 kW/dm3 at 75 kHz with a sustained efficiency of 98.52%. The AMLI with RNSD is established as a highly effective solution for advancing high-power-density converter applications.

Original languageEnglish
Pages (from-to)1-11
Number of pages11
JournalInternational Journal of Integrated Engineering
Volume17
Issue number9
DOIs
Publication statusPublished - 31 Dec 2025

Keywords

  • efficiency
  • Multilevel inverter
  • Pareto-Front curves
  • power density
  • pulse width modulation
  • sinusoidal pulse width modulation

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